The integration of two-dimensional semiconductors with high-κ dielectric materials is crucial for the development of post-silicon electronic devices. The key challenge lies in developing ultra-thin high-κ dielectrics with pristine interfaces and an equivalent oxide thickness (EOT) below 1 nm to extend Moore's Law. Against this backdrop, Researcher Huo Nengjie's team from the School of Electronic Science and Engineering (School of Microelectronics) in the Faculty of Engineering at South China Normal University has made breakthrough progress in high-κ dielectrics and their electronic devices. The related achievements, titled "Controllable growth of MoO₃ dielectrics with sub-1 nm equivalent oxide thickness for 2D electronics," have been published in Nature Communications.

The first author of the paper is Xueming Li, a 2022 master's student from the School of Electronic Science and Engineering (School of Microelectronics) in the Faculty of Engineering, with Researcher Huo Nengjie as the corresponding author. Our university is the sole completing institution. This research has developed a controllable freestanding growth technique for layered MoO₃ dielectric materials, achieving an equivalent oxide thickness (EOT) as low as 0.9 nm and a dielectric constant exceeding 40. It has been successfully applied to two-dimensional electronic devices, promoting the development of high-performance, miniaturized, low-power electronic devices in the post-Moore era.

Breakthrough in Dielectric Performance: Superior Dielectric and Breakdown Characteristics

As the core component of transistors, gate dielectric layers have long been a key research focus in advanced chip manufacturing. Utilizing a "vertical self-growth" technique, the research team has achieved controllable growth of high-κ MoO₃ dielectric with a dielectric constant exceeding 40. This material demonstrates excellent capacitive properties, outstanding breakdown resistance, and superior insulation characteristics, representing a significant breakthrough for the development of future low-power, highly integrated transistors.

Electronic Device Applications: High-Performance Transistors and Vertically-Stacked CMOS Inverters

The vertically-grown MoO₃ achieves an atomically smooth and defect-free surface, thereby preserving both the high dielectric properties of MoO₃ and the intrinsic electrical characteristics of the two-dimensional channel material. MoS₂ transistors utilizing MoO₃ as the high-κ gate dielectric exhibit a high on/off ratio approaching 10⁸, a low subthreshold swing of 78 mV/dec, and a leakage current density below 10⁻⁴ A/cm². Furthermore, by integrating n-type MoS₂ and p-type WSe₂ transistors with MoO₃ as the gate dielectric, vertically-stacked CMOS inverters have been successfully demonstrated. This breakthrough addresses a critical challenge in device scaling and provides new options and solutions for next-generation electronic applications.

This research work was supported by the National Natural Science Foundation of China, the Natural Science Foundation of Guangdong Province, and the Guangdong Provincial Key Laboratory of Chip and Integration Technology. A patent application has been filed for the related technology.

         Link: https://url.scnu.edu.cn/record/view/index.html?key=f642077b1d749eac67af84241220c3c5